ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 467

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.11 Programming Sequence
6430D–ATARM–25-Mar-11
1. Enabling the Main Oscillator:
2. Checking the Main Oscillator Frequency (Optional):
3. Setting PLL and Divider:
4. Selection of Master Clock and Processor Clock
The main oscillator is enabled by setting the MOSCXTEN field in the CKGR_MOR register.
The user can define a start-up time. This can be achieved by writing a value in the
MOSCXTST field in the CKGR_MOR register.
Once this register has been correctly configured, the user must wait for MOSCXTS field in
the PMC_SR register to be set. This can be done either by polling the status register or by
waiting the interrupt line to be raised if the associated interrupt to MOSCXTS has been
enabled in the PMC_IER register.
Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles.
In some situations the user may need an accurate measure of the main clock frequency.
This measure can be accomplished via the CKGR_MCFR register.
Once the MAINFRDY field is set in CKGR_MCFR register, the user may read the MAINF
field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen
slow clock cycles.
All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR
register.
The DIVA field is used to control the divider itself. It must be set to 1 when PLLA is used. By
default, DIVA parameter is set to 0 which means that the divider is turned off.
The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0
and 2047. If MULA is set to 0, PLLA will be turned off, otherwise the PLLA output frequency
is PLLA input frequency multiplied by (MULA + 1).
The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in
the PMC_SR register after CKGR_PLLAR register has been written.
Once the CKGR_PLLA register has been written, the user must wait for the LOCKA bit to be
set in the PMC_SR register. This can be done either by polling the status register or by wait-
ing the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in
the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single
write operation. If at some stage one of the following parameters, MULA, DIVA is modified,
LOCKA bit will go low to indicate that PLLA is not ready yet. When PLLA is locked, LOCKA
will be set again. The user is constrained to wait for LOCKA bit to be set before using the
PLLA output clock.
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values. Master Clock output is prescaler input divided by PRES parameter. By
default, PRES parameter is set to 1 which means that master clock is equal to main clock.
SAM3U Series
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