ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 100

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.10.6
13.10.7
100
SAM3U Series
PC-relative expressions
Conditional execution
All other load and store instructions generate a usage fault exception if they perform an
unaligned access, and therefore their accesses must be address aligned. For more information
about usage faults see
Unaligned accesses are usually slower than aligned accesses. In addition, some memory
regions might not support unaligned accesses. Therefore, ARM recommends that programmers
ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use
the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses,
see
A PC-relative expression or label is a symbol that represents the address of an instruction or lit-
eral data. It is represented in the instruction as the PC value plus or minus a numeric offset. The
assembler calculates the required offset from the label and the address of the current instruc-
tion. If the offset is too big, the assembler produces an error.
Most data processing instructions can optionally update the condition flags in the Application
Program Status Register (APSR) according to the result of the operation, see
gram Status Register” on page
subset. If a flag is not updated, the original value is preserved. See the instruction descriptions
for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another instruc-
tion, either:
Conditional execution is available by using conditional branches or by adding condition code
suffixes to instructions. See
tions to make them conditional instructions. The condition code suffix enables the processor to
test a condition based on the flags. If the condition test of a conditional instruction fails, the
instruction:
Conditional instructions, except for conditional branches, must be inside an If-Then instruction
block. See
Depending on the vendor, the assembler might automatically insert an IT instruction if you have
conditional instructions outside the IT block.
• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current
• For all other instructions that use labels, the value of the PC is the address of the current
• Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
• does not execute
• does not write any value to its destination register
• does not affect any of the flags
• does not generate any exception.
instruction plus 4 bytes.
instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
or minus a number, or an expression of the form [PC, #number].
“Configuration and Control Register” on page
“IT” on page 149
“Fault handling” on page
Table 13-16 on page 101
for more information and restrictions when using the IT instruction.
62. Some instructions update all flags, and some only update a
86.
190.
for a list of the suffixes to add to instruc-
6430D–ATARM–25-Mar-11
“Application Pro-