ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 669

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 34-6. Receiver Overrun
34.4.2.5
Figure 34-7. Parity Error
34.4.2.6
Figure 34-8. Receiver Framing Error
6430D–ATARM–25-Mar-11
RXRDY
OVRE
URXD
RXRDY
URXD
PARE
FRAME
RXRDY
URXD
S
Parity Error
Receiver Framing Error
D0
S
S
D1
D0
D0
D2
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in UART_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in UART_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until
the control register UART_CR is written with the bit RSTSTA at 1.
D1
D1
D3
D2
D2
D4
D3
D3
D5
D4
D4
D6
D5
D5
D7
D6
D6
P
Wrong Parity Bit
D7
D7
stop
P
P
S
Detected at 0
stop
Stop Bit
stop
D0
D1
D2
D3
RSTSTA
RSTSTA
D4
D5
SAM3U Series
D6
D7
P
stop
RSTSTA
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