TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 852

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

I2SMCLK Out
Master mode:
I2S1DATO, I2SxWS hold time
Master mode:
I2S1DATO, I2SxWS delay time
Master mode:
I2S0DATI setup time
Master mode:
I2S0DATI hold time
Master mode:
I2SxMCLK, I2SxSCLK delay time
Slave mode:
I2S1DATO, I2SxWS hold time
Slave mode:
I2S1DATO, I2SxWS delay time
Slave mode:
I2S0DATI setup time
Slave mode
I2S0DATI hold time
I2SxMCLK high level pulse width
I2SxMCLK low level pulse width
I2SxCLK clock output period
I2SxCLK clock input period
I2SxCLK high level pulse width
I2SxCLK low level pulse width
4.3.8
Parameter
I
Note: The “Equation” column in the table shows the specifications under the conditions DVCC3I2S 1.8 to 3.6 V and
2
AC measurement conditions
AC measurement conditions: Load capacitance CL
S
f
The letter “T” used in the equations in the table represents the period of internal bus frequency (f
which is one-half of the CPU clock (f
The letter “t” used in the equations in the table represents the period of frequency (f
Output level: High
Input level: High
DVCC1A
input.
OSCH
DVCC1B
Symbol
f
t
t
f
t
t
t
t
t
t
t
SCKM
HTRM
DTRM
t
t
SCKS
HTRS
DTRS
f
WMH
WML
t
t
DLY1
SRM
HRM
0.9
SRS
HRS
WH
MC
WL
0.7
DVCC1C
DVCC3I2S, Low
DVCC3I2S, Low
0.5 f
0.5 f
0.45 f
0.45 f
0.2 f
0.2 f
TMPA901CM- 851
SCKS
Min
10.0
10.0
333
160
SCKM
t /4
10
10
1.4 to 1.6 V. In slave mode, the stabilization time is required after I2SxCLK
SCKM
SCKS
SCKM
SCKM
2T
Equation
2T
FCLK
). f
0.8 f
0.5 f
0.1
PCLK
SCKM
SCKS
0.3
Max
10.0
25
DVCC3I2S
25 pF
3T
3T 20
16
DVCC3I2S
10
I2SxSCLK.
100MHz
333
160
149
149
186
206
100
178
24
10
10
10
66
10
10
32
96 MHz
333
160
149
149
187
207
100
179
24
10
10
10
66
10
10
32
OSCH
TMPA901CM
2010-07-29
).
Unit
MHz
ns
PCLK
),