TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 107

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

9. DMACSoftBReq (DMAC Software Burst Request Register)
]
]
[Description]
[31:15
[14]
[13:10
[11]
[10]
[9:5]
[4]
[3]
[2]
[1]
[0]
a. <SoftBReq[14:0]>
Bit
Note: Making DMA request by software and a hardware peripheral simultaneously is prohibited.
circuitry is included. ).
DMA burst transfer, the corresponding bit of SoftBReq [14:0] is cleared.
This register is used to set DMA burst transfer requests by software. Upon completion of a
The state of the burst-request is led when leading. (The demand by the peripheral
SoftBReq14
Reserved
SoftBReq11
SoftBReq10
Reserved
SoftBReq4
SoftBReq3
SoftBReq2
SoftBReq1
SoftBReq0
Symbol
Bit
W
W
W
W
W
W
W
W
W
W
pe
R/
R/
R/
R/
R/
R/
R/
R/
R/
R/
Ty
TMPA901CM- 106
d
d
d
Undefine
0y0
Undefine
0y0
0y0
Undefine
0y0
0y0
0y0
0y0
0y0
Reset
Value
Read as undefined. Write as zero.
DMA burst request of LCDDA by software
0y0: Invalid when data write
0y1: Generate a DMA burst request
Read as undefined. Write as zero.
DMA burst request of I
0y0: Invalid when data write
0y1: Generate a DMA burst request
DMA burst request of I
0y0: Invalid when data write
0y1: Generate a DMA burst request
Read as undefined. Write as zero.
DMA burst request of NANDC0 by software
0y0: Invalid when data write
0y1: Generate a DMA burst request
DMA burst request of SSP0 receive by software
0y0: Invalid when data write
0y1: Generate a DMA burst request
DMA burst request of SSP0 transmit by software
0y0: Invalid when data write
0y1: Generate a DMA burst request
DMA burst request of UART0 receive by software
0y0: Invalid when data write
0y1: Generate a DMA burst request
DMA burst request of UART0 transmit by software
0y0: Invalid when data write
0y1: Generate a DMA burst request
Address
2
2
S0 by software
S1 by software
Description
(0xF410_0000) + (0x0020)
TMPA901CM
2010-07-29