TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 780

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[7:6]
[5]
[4]
[3]
[2]
[1:0]
Bit
Mnemonic
HCFS
BLE
CLE
IE
PLE
CBSR
Isochronous
HostController
FunctionalState
ForUSB
BulkListEnable
ControlList
Enable
Enable
PeriodicList
Enable
ControlBulk
ServiceRatio
Field name
TMPA901CM- 779
00:USBRESET
01:USBRESUME
10:USBOPERATIONAL
11:USBSUSPEND
A transition to UsbOperational from another state causes SOF
generation to begin 1 ms later. HCD may determine whether the HC
has begun sending SOFs by reading the StartofFrame field of the
HcInterrupt register.
This field may be changed by the HC only when in the UsbSuspend
state.
The HC may move from the UsbSuspend state to the UsbResume
state after detecting the resume signaling from a downstream port.
The HC enters UsbSuspend after a software reset, whereas it enters
UsbReset after a hardware reset. The latter also resets the Root Hub
and asserts subsequent reset signaling to downstream ports.
This bit is set to enable the processing of the Bulk list in the next
Frame. If cleared by HCD, processing of the Bulk list does not occur
after the next SOF.
The HC checks this bit whenever it determines to process the list.
When disabled, HCD may modify the list. If HcBulkCurrentED is
pointing to an ED to be removed, HCD must advance the pointer by
updating HcBulkCurrentED before re-enabling processing of the list.
This bit is set to enable the processing of the Control list in the next
Frame. If cleared by HCD, processing of the Control list does not occur
after the next SOF. The HC must check this bit whenever it determines
to process the list. When disabled, HCD may modify the list. If
HcControlCurrentED is pointing to an ED to be removed, HCD must
advance the pointer by updating HcControlCurrentED before
re-enabling processing of the list.
This bit is used by HCD to enable/disable processing of isochronous
EDs. While processing the periodic list in a Frame, the HC checks the
status of this bit when it finds an Isochronous ED (F=1). If set
(enabled), the HC continues processing the EDs. If cleared (disabled),
the HC halts processing the periodic list (which now contains only
isochronous EDs) and begins processing the Bulk and Control lists.
The setting of this bit is also valid in the next Frame.
* This product has some restrictions on isochronous transfers.
This bit is set to enable the processing of the periodic list in the next
Frame. If cleared by HCD, processing of the periodic list does not
occur after the next SOF. The HC must check this bit before it starts
processing the list.
This bit specifies the service ratio between Control and Bulk EDs.
Before processing any of the nonperiodic lists, the HC must compare
the ratio specified with its internal count on how many nonempty
Control EDs have been processed, in determining whether to continue
serving another Control ED or switch to Bulk EDs. The internal count
will be retained when crossing the frame boundary.
In case of a reset, HCD is responsible for restoring this value.
CBSR No. of Control EDs over Bulk EDs served
00
01
10
11
1:1
2:1
3:1
4:1
Function
TMPA901CM
2010-07-29