TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 803

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Read/Write
(HCD)
Read/Write
(HC)
Read/Write
(HCD)
Read/Write
(HC)
bit Symbol
Reset state
bit Symbol
Reset state
[31:21]
[20]
[19]
[18]
Bit
22. HcRhPortStatus Register
NumberDownstreamPorts of the HcRhDescriptorA register represents the number of
HcRhPortStatus registers that are implemented in hardware. The lower word is used to
reflect the port status, whereas the upper word reflects the status change bits. Some status
bits are implemented with special write behavior (see below). If a transaction (token
through handshake) is in progress when a write to change port status occurs, the resulting
port status change must be postponed until the transaction completes. Reserved bits
should always be written 0.
The HcRhPortStatus register is used to control and report port events on a per-port basis.
Mnemonic
－
PRSC
OCIC
PSSC
31
15
30
14
Reserved
PortResetStatus
Change
PortOverCurrent
IndicatorChange
PortSuspend
StatusChange
29
13
Reserved
Field name
28
12
27
11
TMPA901CM- 802
Reserved
26
10
This bit is set at the end of the 10-ms port reset signal. HCD writes a 1
to clear this bit. Writing a 0 has no effect.
0: Port reset is not complete
1: Port reset is complete
This bit is valid only if overcurrent conditions are reported on a per-port
basis. This bit is set when Root Hub changes the
PortOverCurrentIndicator bit. HCD writes a 1 to clear this bit. Writing a
0 has no effect.
0: No change in PortOverCurrentIndicator
1: PortOverCurrentIndicator is changed
This bit is set when the full resume sequence is completed. This
sequence includes the 20-s resume pulse, LS EOP, and 3-ms
resynchronization delay. HCD writes a 1 to clear this bit. Writing a 0
has no effect. This bit is also cleared when ResetStatusChange is set.
0: Resume is not completed
1: Resume is completed
LSDA
R/W
R/W
25
9
X
PPS
R/W
R/W
24
8
0
23
7
Reserved
22
6
Address
Function
21
5
PRSC
PRS
R/W
R/W
R/W
R/W
20
4
0
0
(0xF450_0000) + (0x0054)
R/W
R/W
R/W
R/W
OCIC
POCI
19
3
0
0
PSSC
PSS PES CCS
R/W
R/W
R/W
R/W
18
2
0
0
TMPA901CM
2010-07-29
PESC
R/W
R/W
R/W
R/W
17
1
0
0
CSC
R/W
R/W
R/W
R/W
16
0
0
0