TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 438

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.2.4 Terms and Presentation
Assert
Deassert
Word
Byte
UDC2
UDC2AB
Endpoint
Rx-EP
Tx-EP
Endpoint I/F
PVCI I/F
Master transfer
Target device
Master Write transfer
Master Read transfer
Slave transfer
USB_RESET
NULL packet
PHY
Interrupt
: Indicates the signal is active.
: Indicates the signal is inactive.
: 32 bits
: 8 bits
: Indicates the USB2.0 device controller to be connected to UDC2AB.
: This IP: Abbreviation of UDC2-AHB-Bridge
: FIFO held by UDC2 for communication with the USB host. Abbreviated as “EP”.
: Receive endpoint. For the OUT transfer of USB transfer (USB host to USB
: Transmit endpoint. For the IN transfer of USB transfer (USB device to USB host).
: DMA interface dedicated to the endpoints held by UDC2.
: Common interface held by UDC2. Used for accessing the internal registers of
: Indicates that UDC2AB acquires the bus right to make transfer.
: Indicates the device (such as memories) to be accessed by UDC2AB with master
: Indicates the transfer with Rx-EP made by UDC2AB.
: Indicates the master transfer with Tx-EP made by UDC2AB.
: Indicates the transfer made by other devices than UDC2AB targeted at UDC2AB.
: Bus reset sent from the USB host. "Reset Signaling" in the USB specification.
: 0-length data to be transferred on USB.
: USB 2.0 PHY
: Indicates the INTS [21] output signal. Descriptions like "Assert xx interruption" in
device).
this document are based on the assumption that the relevant bit of the Interrupt
Enable resistor is enabled. See section 3.16.2.7 “Interrupt Signal (INTS[21])" for
more information.
UDC2
transfer.
TMPA901CM- 437
TMPA901CM
2010-07-29