TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 394

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.14.6
Figure 3.14.11 Number of clocks for data transfer according to I2C0CR1<BC> and I2C0CR1<ACK>
I2CINT0 interrupt request
I2C0CL
3.14.6.1 Slave Address Match Detection and General Call Detection
3.14.6.2 Number of Clocks for Data Transfer and Acknowledge Operation
Note:
call detection in slave mode.
call detection.
call detection. The slave device ignores slave addresses and general calls sent from the
master and returns no acknowledgement. I2CINT0 interrupt requests are not generated.
Functions
(1) Number of clocks for data transfer
general call detection.
For a slave device, the following setting is made for slave address match detection and
I2C0CR1<NOACK> enables or disables the slave address match detection and general
Clearing I2C0CR1<NOACK> to 0 enables the slave address match detection and general
Setting I2C0CR1<NOACK> to 1 disables the slave address match detection and general
In master mode, I2C0CR1<NOACK> is ignored and has no effect on operation.
1
I2C0CR1<ACK>.
then generates an acknowledge clock and an I2CINT0 interrupt request.
acknowledge clock and generates an I2CINT0 interrupt request.
then generates an I2CINT0 interrupt request.
I2CINT0 interrupt request.
low during the acknowledge clock period from the master to request the transfer of the
next word. Conversely, by holding I2C0DA high during the acknowledge clock period
from the master, the receiver device can indicate that it is not requesting the next
word.
and slave must be configured for 8-bit transfer with acknowledge enabled.
If I2C0CR1<NOACK> is cleared to 0 during data transfer in slave mode, it remains 1 and an acknowledge
signal is returned for the transferred data.
The number of clocks for data transfer is set through I2C0CR1<BC> and
Setting I2C0CR1<ACK> to 1 enables acknowledge operation.
The master device generates clocks for the number of data bits to be transferred, and
Clearing I2C0CR1<ACK> to 0 disables acknowledge operation.
The master device generates clocks for the number of data bits to be transferred, and
The slave device counts clocks for the number of data bits, and then generates an
When acknowledge operation is enabled in receiver mode, the device pulls I2C0DA
During address transmission (before a start condition is generated), both the master
The slave device counts clocks for the number of data bits, and then counts an
2
I2C0CR1<BC> = 0y110,
I2C0CR1<ACK> = 0
3
4
TMPA901CM- 393
5
6
1
I2C0CR1<BC> = 0y011,
I2C0CR1<ACK> = 1
2
3
4
TMPA901CM
2010-07-29