TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 292

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Interrupt request signal
(1 shot)
[Description]
a. <xxxIC>, <xxxEIS>, <xxxRIS>, <xxxIE>
occurs when the status of the monitored NDRB pin changes from Busy to Ready and a
Reed-Solomon calculation end interrupt that occurs when Reed-Solomon calculation of
address and data ends. The NDFC asserts one interrupt request obtained by ORing these
two interrupt requests to the interrupt controller. Therefore, the register contents check
during interrupt processing and the processing appropriate to the individual interrupt
source are required.
These are 4-bit registers to support two types of interrupts: a READY interrupt that
The following figure shows the relationship between these registers:
<***IC> : Clear register (WO)
D Q
<***RIS> : Raw interrupt request status (RO)
<***IE> : Enable register (R/W)
D Q
D Q
TMPA901CM- 291
<***EIS> : Masked interrupt request status (RO)
D Q
TMPA901CM
2010-07-29