TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 575

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.17 I
Transmit/Receive
Data formats
FIFO buffer
Data length
interface can support the implementation of a digital audio system.
Pins used
Interrupts
2
Channel
Modes
Clocks
S (Inter-IC Sound)
The TMPA901CM contains a serial input/output circuit compliant with the I
By connecting an external audio LSI, such as an AD converter or DA converter, the I
The I
2
S of this LSI has the following characteristics:
(1) I2S0SCLK (clock input/output)
(2) I2S0DATI (data input)
(3) I2S0WS (word select input/output)
(4) I2S0MCLK (master clock output)
(1) I2SWS can be set to 1/256, 1/384 or 1/512 of the master clock.
(2) the internal clock (X1) can be used as the source clock.
(3) The master clock can be generated by dividing down the source clock to 1, 1/2 or 1/4.
FIFO underflow interrupt
FIFO overflow interrupt
Table 3.17.1 I
Receive only
2 × 8 words
16 bits only
Channel 0
(1) I
(2) Stereo/monaural
(3) MSB first/LSB first selectable
(4) Left-justified supported (synchronous to WS, no delay)
2
S format-compliant
TMPA901CM- 574
2
S operation characteristics
Full-duplex master mode
Full-duplex slave mode
Clock through mode
(1) I2S1DATO (data output)
FIFO underflow interrupt
FIFO overflow interrupt
Transmit only
2 × 8 words
16 bits only
Channel 1
2
S format.
TMPA901CM
2010-07-29
2
S