TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 455

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31]
[30]
[29:8]
[7:2]
[1:0]
Bit
[Description]
dmardreq
dmardclr
dmardadr
a. <dmardreq>
b. <dmardclr>
Master Read Current Address register
Timeout Count register
Note: As accesses to this register become unavailable when the clock (= CLK_U) supply from PHY is stopped with
6. DMACRDREQ (DMAC Read Request register)
Symbol
The bit for requesting read access to the DMAC registers. Setting this bit to 1 will make a
read access to the address specified by dmardadr. When the read access is complete and
the read value is stored in the DMAC Read Value register, this bit will be automatically
cleared and the int_dmac_reg_rd bit of Interrupt Status register will be set to 1.
0y0: No operation
0y1: Issue read request
The bit for forcibly clearing the register read access request associated with DMAC.
Setting this bit to 1 will forcibly stop the register read access request by dmardreq and the
value of dmardreq will be cleared to 0. After the forced clearing completes, this bit will be
automatically cleared.
0y0: No operation
0y1: Issue forced clearing
Bit
UDC2 suspended, no access should be made. If this register is accessed when the phy_suspend bit of Power
Detect Control register is set to 1, an AHB error will be returned.
This register is used to issue read requests for reading the following registers:
The read value will be saved in the DMAC Read Value register.
R/W1S
R/W1S
R/W
Type
0y0
0y0
Undefined
0y000000
Undefined
TMPA901CM- 454
Reset
Value
Register read request & busy
0y0: No operation
0y1: Issue read request
0y0: No operation
0y1: Issue forced clearing
Read as undefined. Write as zero.
Read request register address (upper 6 bits) select
0x48: Read the Master Write Current Address register
0x58: Read the Master Read Current Address register
0x88: Read the Timeout Count register
Read as undefined. Write as zero.
Read request clear
Address = (0xF440_0000) + (0x0014)
Description
TMPA901CM
2010-07-29