TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 567

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(2)
(UDC2-Output)
DDP/DDM
suspend_x
Suspend Operation in FS Mode
T0: End of bus activity
T1: Recognition of suspend (3 ms after T0)
T2: Remote wakeup start enable (5 ms after T0)
T3: Transition to suspend state (10 ms after T0)
When the end of bus activity from the host (the end of packet) is detected, UDC2 starts
counting to recognize suspend.
When the “FS-J” is detected for more than 3 ms after T0, UDC2 recognizes suspend and
drives suspend_x “L”.
Resume operation from the device (remote wakeup) is enabled 5 ms after T0. For details,
refer to “4(2) Resume Operation by the Device (Remote Wakeup)”
The device must enter the suspend state no later than 10 ms after T0. Processes required
of the device system to enter the suspend state, such as stopping the clock supply from
USB 2.0 PHY, must be performed during this period.
time
Activity
Last
Figure 3.16.30 Suspend operation timing in FS mode
T0
TMPA901CM- 566
T1
T2
”J” State
TMPA901CM
T3
2010-07-29