TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 810

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.25.8
1.
2.
3.
4.
<Conditions>
should not be linked.
Restrictions on the USB Host Controller
For an isochronous transfer, a frame number to be transferred is defined in an Isochronous
Transfer Descriptor (ITD). However, when frame numbers are not synchronized between
the Host and software, and if the descriptor to be executed with a previous frame is
scheduled later, the host determines that a time error has occurred and writes back
DATAOVERRUN to the CC field of the ITD. However, if the following conditions are met,
the host will write back inappropriate status (NOERROR).
For a low-speed IN transfer by the host, the USB 2.0 Specification defines the inter-packet
delay (the time from when the Host receives a data packet to when the host transfers a
handshake packet) as less than 7.5 bit times. In this product, however, the inter-packet
delay is about 9.2 bit times in the worst case.
If a fatal error occurs on the USB system and the host detects this error (e.g., Master Abort,
Target Abort, etc. on the PCI bus), the OHCI core sets the UnrecoverableError (UE) bit in
the HcInterruptStatus register.
At this time, if the Unrecoverable Error (UE) bit is set and the UE bit in the
HcInterruptEnable register is set, a hardware interrupt is generated.
After this interrupt is detected, a software reset (HcCommandStatus.HCR = 1’b1) is
required to recover from the UE state, and the host then moves to the SUSPEND state.
After the software reset, OHCI registers are initialized. If a remote wake-up occurs on the
device, the host remains in the SUSPEND state.
When the remote wake-up function is to be used, a program for recovering from the
SUSPEND state must be implemented.
When HcRhDescriptorA.NPS[9] is set to 1’b1 when an overcurrent is occurred,
PortResetStatus.PRS[4] and PortSuspendStatus.PSS[2] of the HcRhPortStatus register is
not
HcRhDescriptorB.DR[PortNo] = 1’b1.
Programming examples:
The above problem occurs if both the following two conditions are met:
1. ITD.FC[2:0] = R[2:0]
2. ITD.FC[2:0] < R[15:0]
where ITD.FC indicates the number of times an ITD is executed, and
R = HcFmNumber (current frame number) – ITD.SF (transfer start frame number).
Make sure that each ITD is synchronized to the current frame number. If not, this ITD
1)
2)
cleared.
After initializing OHCI registers by a software reset, set a value other than
USBSUSPEND (2’b11) to the HcControl.HCFS field.
When a remote wake-up is detected, the HcInterruptStatus.RD bit is set to 1’b1.
After detecting this interrupt, set a value other than USBSUSPEND (2’b11) to
the HcControl.HCFS field.
Therefore,
TMPA901CM- 809
do
not
set
HcRhDescriptorA.NPS[9]
=
TMPA901CM
2010-07-29
1'b1
and