TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 412

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.15.2
types of synchronous serial interfaces.
transmit and receive paths are buffered with a 16-bit wide, 8 locations deep independent
transmit FIFO and receive FIFO in transmit mode and receive mode, respectively. Serial data
is transmitted on SP0DO and received on SP0DI.
the input clock PCLK. The SSP operating mode, frame format and size are programmed
through the control registers SSP0CR0 and SSP0CR1.
The SSP is an interface for serial communication with peripheral devices that have three
The SSP performs serial-to-parallel conversion on data received from a peripheral device. The
The SSP contains a programmable prescaler to generate the serial output clock SP0CLK from
free-running counters is used to provide the serial output clock SP0CLK.
PCLK by a factor of 2 to 254 in steps of two. By not using the least significant bit of the
SSP0CPSR register, division by an odd number cannot be programmed.
one to the value programmed in the SSP0CR0 control register, to give the master output
clock SP0CLK.
SSP Overview
(1) Clock prescaler
When configured as a master, a clock prescaler comprising two serially linked
This clock prescaler can be programmed, through the SSP0CPSR register, to divide
The output of the prescaler is further divided by a factor of 1 to 256, obtained by adding
Bit rate = f
PCLK
(Depends on the setting.)
PCLK
CPSDVSR [7:1]
Clock initial value
Clock prescaler
Figure 3.15.2 Block diagram of Clock prescaler
/ (CPSDVSR
TMPA901CM- 411
SSPCLKDIV
(1 + SCR))
(SCR [7:0] + 1)
Toggle circuit
Divide circuit
Clock inversion trigger
SPxCLK
TMPA901CM
2010-07-29