TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 434

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.2
USB
Controller (hereinafter “UDC2”) and AHB. UDC2AB has the DMA controller that supports
the AHB master transfer and controls transfer between the specified address on AHB and the
Endpoint-FIFO (Endpoint I/F) inside UDC2.
UDC2AB AHB Bus Bridge
UDC2AB (UDC2 AHB Bridge) is the bridge circuit between Toshiba USB-Spec 2.0 Device
USB
PHY
2.0
(1) Connection with UDC2
(2) AHB functions
connected. However, the DMA controller in UDC2AB (AHB master function) can be
connected with only one Rx-EP and one Tx-EP. Accesses to other endpoints (including
EP0) should be made through PVCI I/F of UDC2 using the AHB slave function. Please
note the EPx_FIFO register of a UDC2 endpoint in master transfer with the DMA
controller cannot be accessed through PVCI I/F.
read function will be an odd number, there will be some restrictions on the usage. See
section 3.16.2.9 “(3)Setting the maximum packet size in Master Read transfers” for
more information.
3.16.2.1 Functions and Features
UDC2AB has the following functions and features:
There is no specific restriction on the endpoint configuration for the UDC2 to be
If the maximum packet size of the endpoint to be connected with the AHB master
AHB Master and AHB Slave functions are provided.
Figure 3.16.2 UDC2AB block diagram
UDC2
TMPA901CM- 433
PVCI Ctrl
EPINT
EPRX
EPTX
EP0
DMAC_W0
DMAC_R0
AHB Slave
UDC2AB
Master
Slave
AHB
AHB
I/F
I/F
AHB
TMPA901CM
2010-07-29