TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 395

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Note:
and the I2C0CR1<BC> and I2C0CR1<ACK> settings.
data. At other times, <BC> retains the set value.
Table 3.14.3 shows the relationship between the number of clocks for data transfer
I2C0CR1<BC> is cleared to 0y000 by a start condition.
This means that the slave address and direction bit are always transferred as 8-bit
A slave address must be transmitted/received with I2C0CR1<ACK> set to 1. If I2C0CR1<ACK> is
cleared, the slave address match detection and direction bit detection cannot be performed properly.
BC[2:0]
000
001
010
011
100
101
110
111
Table 3.14.3 Number of clocks for data transfer
Data length
Acknowledge operation (I2C0CR1<ACK>)
8
1
2
3
4
5
6
7
0y0: Disabled
TMPA901CM- 394
Number of
clocks
8
1
2
3
4
5
6
7
Data length
8
1
2
3
4
5
6
7
0y1: Enabled
Number of
clocks
9
2
3
4
5
6
7
8
TMPA901CM
2010-07-29