TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 277

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

FIFO to be writen by the DMAC
NDFMCR1<ALS>
register
NDWEn
FIFO used for write to the
NAND-Flash
DMAC end interrupt
Note: Write operation to the NAND-Flash memory is not terminated by the Autoload function of the NDFC at the time
full, the Autoload function is suspended for that duration.
If DMAC cannot be write the data to FIFO of the NDFC when FIFO-0 and FIFO-1 are
(2) Write 1 to the NDFMCR1<SELAL> register and 1 to the NDFMCR1<ALS>
of assertion of a DMAC end interrupt. Ensure that the NDFMCR1<ALS>
processing and then execute the next process (processing of the ECC).
and FIFO-1 are empty, to have the DMA controller transfer data from the built-in RAM
to FIFO-0 and FIFO-1.
terminated, the NDFC uses the FIFO-0 data to start a data write cycle to NAND-Flash.
Each time the NDFC writes data, it generates the ECC by entering the data to either
Hamming Code ECC calculator or Reed-Solomon ECC calculator depending on the
setting of the NDFMCR1<ECCS> register. When FIFO-0 becomes empty, the FIFO-1
takes over the data extraction for continued data write.
FIFO-0’s becoming empty to request the data transfer from the built-in RAM to
FIFO-0.
FIFOs in this way.
termination interrupt and the CPU uses the interrupt to start the next process. The
following shows a conceptual timing chart of the data write timing by DMA.
When step (2) is performed, the NDFC asserts a DMA request, because both FIFO-0
When the data transfer from the DMA controller to FIFO-0 and FIFO-1 is
In addition, the NDFC asserts a DMA transfer request to the DMAC at the time of
Data can be written efficiently at a higher speed by switching between two 16-byte
When a total of 512 bytes of data has been written, the DMAC asserts a DMA
register.
0
1
1
2
0
16
TMPA901CM- 276
17
0
18
1
32
33
1
34
0
48
1
0 during the DMAC end interrupt
497
498
1
512
TMPA901CM
2010-07-29