TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 566

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3. Suspend Operation *2
(1)
suspend_x
(UDC2-Output)
xcvr_select
(UDC2-Output)
term_select
(UDC2-Output)
DDP/DDM
Suspend Operation in HS Mode
T0: End of bus activity
T1: Transition to FS mode (3.0 ms to 3.125 ms after T0)
T2: Recognition of suspend (100 µs to 875 s after T1)
T3: Remote wakeup start enable (5 ms after T0)
T4: Transition to suspend state (10 ms after T0)
When the end of bus activity from the host (the end of packet) is detected, UDC2 starts
counting to recognize suspend/reset.
When SE0 is detected for more than 3 ms after T0, UDC2 enters FS mode and drives
xcvr_select and term_select “H”. (This makes USB 2.0 PHY enable DDP pull-up.) At this
point, UDC2 cannot determine whether the host is initiating suspend or reset operation.
UDC2 recognizes suspend and drives suspend_x “L”. When the line state does not change
to “J” and remains “SE0”, UDC2 prepares for reset instead of suspend. In this case, refer
to “2. Reset Operation”.
Resume operation from the device (remote wakeup) is enabled 5 ms after T0. For details,
refer to section “4.(2) Resume Operation by the Device (Remote Wakeup)”.
The device must enter the suspend state no later than 10 ms after T0. Processes required
of the device system to enter the suspend state, such as stopping the clock supply from
USB 2.0 PHY, must be performed during this period.
When the “J” state is detected on the DDP/DDM line in approximately 110 µs after T1,
time
Last
Activity
Figure 3.16.29 Suspend operation timing in HS mode
T0
SE0
TMPA901CM- 565
T1
T2
T3
“J” State
TMPA901CM
2010-07-29
T4