TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 835

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Symbol
No.
4.3.2
VIX
10 CKE set-up time
11 Command set-up time
12 Command hold time
13 Data Setup Time
14 Data Hold Time
15 DMCDDM Setup Time
16 DMCDDM Hold Time
17
1 DMCDCLKP/ DMCDCLKN cycle time Note)
2 DMCDCLKP&DMCDCLKN Clock Skew time
3 CLK Differential Crosspoint cycle
4 CLK Differential Crosspoint cycle
5
6
7 DQS to Data Skew time
8 Address set-up time
9 Address hold time
DMCDDQSx
Access time from CLK(CL* 3)
Data
Access time from CLK(CL* 3)
Write command to 1'st DQS Latching
Transition
AC Differential Cross point Voltage
DDR SDRAM Controller AC Electrical Characteristics
Note 1: Only DDR SDRAM devices of LVCMOS type are supported. DDR SDRAM devices of SSTIL (2.5 V) type are
Note 2: The “Equation” column in the table shows the specifications under the conditions DVCCM
*CL
Note: The internal bus cycle is T=10ns minimum value when the guaranteed temperature is 0 to 70 degree.
The internal bus cycle is T=13.3ns minimum value when the guaranteed temperature is -20 to 85 degree.
AC measurement conditions
In case of DDR_SDRAM, CL number counting method is defferent with SDR_SDRAM.
Memory controller CL number
The letter “T” used in the equations in the table represents the period of internal bus frequency (f
which is one-half of the CPU clock (f
Output level: High
Input level: High
Clock output Differential level (VOD): VOD
Clock output Differential Crosspoint level (VOX): High
CAS latency
not supported.
DVCC1A
Parameter
Parameter
DVCC1B
0.9
0.7
DVCC1C
DVCCM, Low
DVCCM, Low
0.4
( DDR_SDRAM’s CL Number ) – 1
TMPA901CM- 834
Min
Symbol
1.4 to 1.6 V.
DVCCM
t
t
DQSQ
t
t
t
DQSS
t
t
CMS
CMH
t
t
t
t
t
t
CKS
t
t
t
AC1
AC2
CH
DH
MS
MH
CK
CL
AS
AH
DS
FCLK
).
0.1
0.25T - 1.5
0.25T - 1.5
0.25T - 1.5
0.25T - 1.5
0.3
0.5T - 3.0
0.5T - 0.5
0.5T - 0.5
0.5T - 3.0
0.5T - 3.0
0.5T - 3.0
0.5T - 3.0
0.75T
-0.35
Min
0.6
Typ.
T
0
DVCCM
Equation
DVCCM
DVCCM
2T-13.5
2T-13.5
1.25T
Max
0.35
0.6
0.7
0.6
Max
DVCCM
DVCCM, Low
7.50 to 12.5 7.80 to 13.0
MHz
100
4.5
4.5
6.5
6.5
0.7
2.0
2.0
2.0
2.0
2.0
1.0
1.0
1.0
1.0
10
Unit
0.4
MHz
10.4
96
4.7
4.7
7.3
7.3
0.7
2.2
2.2
2.2
2.2
2.2
1.1
1.1
1.1
1.1
1.7
DVCCM
1.7 to 1.9 V and
DVCCM
TMPA901CM
Condition
2010-07-29
Unit
ns
1.9V
HCLK
),