TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 418

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TMPA901CMXBG

Manufacturer Part Number
TMPA901CMXBG
Description
Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
Manufacturer
Toshiba
Datasheet

Specifications of TMPA901CMXBG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
-
Rom Type
ROMless
Ram (kbytes)
32
Number Of Pins
177
Package
BGA
Vcc
3V
Tft Lcd Controller
Y
Touchscreen Controller
Y
Usb Host Fs With Phy
Y
Usb Device Hs With Phy
Y
Sd Host Controller
-
Cmos Image Sensor Interface
-
I2s
1
Ssp (ch) Spi
1
I2mc/sio (ch)
1
Uart/sio (ch)
2
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
8
10-bit Ad Converter
4
12-bit Da Converter
-
16-bit Timer / Counter
6
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
Y
Low-power Modes
Y
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPA901CMXBG
Manufacturer:
Toshiba
Quantity:
10 000
Note1)
Note2)
slave select. The main feature of the SPI format is that the operation timing of
SP0CLK is programmable through the <SPO> and <SPH> bits in the SSP0CR0 control
register.
SSP0CR0<SPO>
SSP0CR0<SPH>
SPI operation examples:
2) SPI
SSP0CR0<SPO> specifies the SP0CLK level during idle periods.
<SPO>
<SPO>
SSP0CR0<SPH> selects the clock edge for latching data.
SSP0CR0<SPH>
SSP0CR0<SPH>
SPI (single transfer, <SPO>
The SPI interface is a four-wire interface where the SP0FSS signal behaves as a
When transmission is disable , SP0DO terminal doesn’t output and is high impedance status. This
terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high
impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage
level.
SP0CLK
SP0FSS
SP0DO
SP0DI
1: SP0CLK is held High.
0: SP0CLK is held Low.
Hi-Z(Note1)
Hi-Z(Note2)
0: Data is latched on the first clock edge.
1: Data is latched on the second clock edge.
TMPA901CM- 417
MSB
MSB
0 & <SPH>
0)
LSB
LSB
Hi-Z(Note2)
Hi-Z(Note1)
TMPA901CM
2010-07-29

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