TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 114

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[Description]
a. <I>
b. Prot[3]
c.
d. Prot[1]
e. DI
f.
g. D
The description below applies to all channels.
Control cache permission HPROT[3]
0y0: Noncacheable
0y1: Cacheable
Control buffer permission HPROT[2]
0y0: Nonbufferable
0y1: Bufferable
Control privileged mode HPROT[1]
0y0: User mode
0y1: Privileged mode
Increment the transfer destination address
0y0: Do not increment
0y1: Increment
Increment the transfer source address
0y0: Do not increment
0y1: Increment
Transfer destination AHB Master
0y0: DMA1
0y1: DMA2
It is enable register of terminal count interrupt.
Terminal count interrupt is generated by setting <I>=1 and DAMCCxConfiguration
Register<ITC>=1.This bit is set to enable in DMAC configuration flow of the final transfer
when using Scatter/gather function, and it is possible to generate terminal count interrupt
when the only final transfer is performed.
To generate an interrupt at transferring, this bit also must be set to enable by setting to
“1”.
Prot[2]
SI
TMPA901CM- 113
TMPA901CM
2010-07-29