TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 101

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3. DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register)
[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[Description]
a. <IntTCClear[7:0]>
Bit
Writing 1 to each bit of this register clears the corresponding bit in the DMACIntTCStatus
register.
IntTCClear7
IntTCClear6
IntTCClear5
IntTCClear4
IntTCClear3
IntTCClear2
IntTCClear1
IntTCClear0
Symbol
Bit
WO
WO
WO
WO
WO
WO
WO
WO
Type
TMPA901CM- 100
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Reset
Value
Read as undefined. Write as zero.
DMAC channel 7 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 6 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 5 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 4 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 3 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 2 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 1 terminal count interrupt clear
0y0 Invalid
0y1 Clear
DMAC channel 0 terminal count interrupt clear
0y0 Invalid
0y1 Clear
Address
Description
(0xF410_0000) + (0x0008)
TMPA901CM
2010-07-29