TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 285

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[Description]
used, this bit should be set to 0.
circuit and a circuit to calculate the error address and error bit position from the ECC.
series. If these operations need to be performed in parallel, the intermediate code used
for error calculation must be latched while the calculation is being performed.
code generated from the ECC for written data and the ECC for read data to calculate
the error address and error bit position.
transferred to the error calculator even if the ECC generator updates the ECC, thus
allowing the ECC generator to generate the ECC for another page while the ECC
calculator is calculating the error address and error bit position. At this time, the ECC
generator can perform both Write and Read operations.
calculator are updated sequentially as the data in the ECC generator is updated.
used, this bit should be set to 0.
ECC read from the NDECCRDn register is written to the redundant area of the
NAND-Flash memory. For a read operation, this bit should be set to 0 (for Read). Then,
valid data is read from the NAND-Flash memory and the ECC written in the
redundant area of the NAND-Flash memory is read to generate an intermediate code
for calculating the error address and error bit position.
a. <RSECCL>
b. <RSEDN>
The <RSECCL> bit is used only for Reed-Solomon codes. When Hamming codes are
The Reed-Solomon processing unit is comprised of two circuits: an ECC generating
No special care is needed if ECC generation and error calculation are performed in
The <RSECCL> bit is provided to enable the latch operation for the intermediate
When <RSECCL> is set to 1, the intermediate code is latched so that no ECC is
When <RSECCL> is set to 0 the latch is released and the contents of the ECC
The <RSEDN> bit is used only for Reed-Solomon codes. When Hamming codes are
For a write operation, this bit should be set to 1 (for write) to generate ECC. The
Flow of data
TMPA901CM- 284
Reed-Solomon
Reed-Solomon
F/F 80 bits
ECC
ECC
<RSECCL>
<RSECCL>
NDECCRDn
register
1 Latch_ON
0 Latch_OFF
TMPA901CM
2010-07-29