TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 458

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31]
[30]
[29:10]
[9:2]
[1:0]
Bit
[Description]
udc2rdreq
udc2rdclr
udc2rdadr
a. <udc2rdreq>
b. <udc2rdclr>
c.
8. UDC2RDREQ (UDC2 Read Request register)
Symbol
The bit for requesting read access to the UDC2 registers. Setting this bit to 1 will make a
read access to the address set in the udc2rdadr bit. When the read access is complete and
the read value is set to UDC2 Read Value register, this bit will be automatically cleared
and the UDINTSTS<int_udc2_reg_rd> bit of Interrupt Status register will be set to 1.
During a write access to UDC2 registers, it works as a status bit which indicates the
access being made to display the value of 1. Subsequent accesses to UDC2 registers
should not be made while this bit is set to 1.
0y0: No operation
0y1: Issue read request
The bit for forcibly clearing the read/write access request of UDC2 registers. Setting this
bit to 1 will forcibly stop the register read request/UDC2 write access by udc2rdreq and
the value of udc2rdreq will be 0. After the forced clearing completes, this bit will be
automatically cleared to 0. When interrupted, the read and write values during the access
will not be secured.
0y0: No operation
0y1: Issue forced clearing
<udc2rdadr>
Sets the address of the UDC2 register (upper 8 bits) to be read. Regarding registor
address, please refer to “Table 3.16.2 Register map”.Between 0x0200 to 0x0334 that is the
offset address of this register map corresponds.It should be set in combination with the
udc2rdreq bit mentioned above.
will be saved in the UDC2 Read Value register.
Bit
The register for issuing read requests when reading UDC2 registers. The read value
R/W1S
R/W1S
R/W
Type
0y0
0y0
Undefined
0x00
Undefined
TMPA901CM- 457
Reset
Value
Register read request & busy
0y0: No operation
0y1: Issue read request
Read request clear
0y0: No operation
0y1: Issue forced clearing
Read as undefined. Write as zero.
The address of the UDC2 register that issues the read
request
Read as undefined. Write as zero.
Address = (0xF440_0000) + (0x001C)
Description
TMPA901CM
2010-07-29