TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 600

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:16]
[15:0]
[31:16]
[15:0]
[Description]
[Description]
a. <Left[15:0]>, <Right[15:0]>
a. <Left[15:0]>, <Right[15:0]>
Bit
Bit
Note1: this register is write-only.
Note2: this register can be accessed from CPU/DMAC as Master.
Note1: this register is read-only.
Note2: this register can be accessed from CPU/DMAC as Master.
17. I2STDAT (Transmit FIFO Window DMA Target Register)
18. I2SRDAT (Receive FIFO Window Target Register)
The set data in this register is written into transmit FIFO, refer to Note 2.
Stereo audio data is set simultaneously with upper data as left channel data and lower
data as right channel data. Data can be written to any address in a range of 0xF2041000
to 0xF2041FFF, and is sequentially stored in the FIFO as it is written. This register does
not support read operations.
To read register data, the data is sequentially read out from receive FIFO, refer to Note 2.
Stereo audio data is input simultaneously with upper data as left channel data and lower
data as right channel data. Data can be read from any address in a range of 0xF2042000
to 0xF2042FFF, and is sequentially read out from the FIFO.
Left[15:0]
Right[15:0]
Left[15:0]
Right[15:0]
Bit Symbol
Bit Symbol
TMPA901CM- 599
WO
WO
RO
RO
Type
Type
0x0000
0x0000
0x0000
0x0000
Reset
Reset
Value
Value
I2STx left audio data [15:0]
I2STx right audio data [15:0]
I2SRx left audio data [15:0]
I2SRx right audio data [15:0]
Address
Address
Description
Description
(0xF204_2000) + (0x0000)
(0xF204_1000) + (0x0000)
TMPA901CM
2010-07-29