TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 525

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

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[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
[Description]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
m_ep3
m_ep2
m_ep1
m_ep0
a. <m_ep[3:0]>
Note: Will be cleared by writing 1 to the relevant bits.
Symbol
Mask control of flag output
Sets whether or not to output flags of INT_EP and INT_RX_DATA0 registers to the int_ep
pin and the int_rx_zero pin respectively. When an EP is masked, each bit of INT_EP
register will be set when the transfer of the relevant EP has successfully finished, but the
int_ep pin will not be asserted. Similarly, when an EP is masked, each bit of
INT_RX_DATA0 register will be set when Zero-Length data is received at the relevant EP,
but the int_rx_zero pin will not be asserted. However, bit 0 is only valid for
INT_RX_DATA0 register.
0y0: Enable (output)
0y1: Disable (no output)
3.
Bit
UD2INTEPMSK (INT_EP_MASK register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Reset
Value
TMPA901CM- 524
Read as undefined. Write as zero.
Mask control of flag output
0y0: Enable (output)
0y1: Disable (no output)
Description
Address = (0xF440_0000) + (0x0228)
TMPA901CM
2010-07-29