TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 784

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[3]
[2]
[1]
[0]
Bit
Mnemonic
RD
SF
WDH
SO
ResumeDetected
StartofFrame
WritebackDone
Head
Scheduling
Overrun
Field name
TMPA901CM- 783
This bit is set when the HC detects that a device on USB is asserting
resume signaling. This is the transition from no resume signaling to
resume signaling causing this bit to be set. This bit is not set when
HCD sets the UsbResume state.
This bit is set by the HC at each start of a frame and after the update of
HccaFrameNumber. The HC also generates a SOF token at the same
time.
This bit is set immediately after the HC writes HcDoneHead to
HccaDoneHead. Further updates of the HccaDoneHead will not occur
until this bit is cleared. HCD should only clear this bit after it saves the
content of HccaDoneHead.
This bit is set when the USB schedule for the current Frame overruns
and after the update of HccaFrameNumber. A scheduling overrun will
also cause the SchedulingOverrunCount of HcCommandStatus to be
incremented.
Function
TMPA901CM
2010-07-29