TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 731

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3. WdogControl (Watchdog control register)
4. WdogIntClr (Clears the watchdog interrupt)
[31:2]
[1]
[0]
[31:0]
[Description]
[Description]
a. <RESEN>
b. <INTEN>
a. <WDTINTCLR>
Bit
Bit
0y1: Enables the WDT counter and the WDT interrupt. When this bit is set to 1, the
Writing any value to this register clears the WDT interrupt and loads the value set in the
WdogLoad register into the WDT counter.
Controls the WDT reset output. Time until releasing reset is after PCLK 5 clocks.
RESEN
INTEN
WDTINTCLR
value set in the WdogLoad register is loaded into the WDT counter and the counter
starts decrementing.
Symbol
Symbol
Bit
Bit
R/W
R/W
WO
Type
Type
TMPA901CM- 730
Undefined
0y0
0y0
Undefined
Reset
Reset
Value
Value
Read as undefined. Write as zero.
WDT reset output enable
0y0: Disable
0y1: Enable
WDT counter and interrupt enable
0y0: Disable
0y1: Enable
WDT interrupt clear
(Writing any value clears the interrupt.)
Address
Address
(0xF001_0000) + (0x0008)
(0xF001_0000) + (0x000C)
Description
Description
TMPA901CM
2010-07-29