TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 205

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(3) SMC Function
completed.
memory. Refer to SMC register of MPMC, smc_set_opmode_3 (SMC Set Opmode
Register).
configuration registers.
Note: In case of not having any page mode methods, e.g. NOR Flash, it is unnecessary to set burst align.
(a) APB slave I/F
(b) Format
(c) Memory manager operation
(d) Memory I/F operation
The APB slave I/F adds a wait state for all reads and writes
More than one wait state is generated in the following case:
Outstanding direct commands
The burst align settings are necessary in order to support asynchronous page mode
The memory manager controls the SMC state and manages update of chip
The memory I/F issues commands and controls their timings.
Memory burst length: Supported memory burst transfer length is 4 beats.
A memory command is received, but the previous memory command has not been
1. Hazard processing
2. Access to the SRAM memory
actual access procedure to memory is executed in the instruction order.
write data will be stored temporary into independent buffer and be executing by
priority circuit. Therefore, the read and the write instruction may switch
execution sequence. So please coordinate a variety of sequences, e.g. making an
enough time for next instruction, checking whether or not previous execution is
finished, the common-use memory data uses the internal memory and so on.
When selfsame stand-alone bus master access to an external memory, the
However, if multiple bus master access to an external memory, the read and
Standard SRAM access
Memory address shifting
Memory burst alignment
TMPA901CM-204
TMPA901CM
2010-07-29