TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 483

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.2.9 Master Transfer Operation
Note 1: About short packets
Note 2: About int_mr_end_add interrupt
(1) Master Read transfer
If the transfer size (Master Read End Address - Master Read Start Address + 1) is not the same size as the
Max packet size, the last IN transfer will be the transfer of short packets.
Example:
Transfers will take place in:
1st time: 512 bytes → 2nd time: 512 bytes → 3rd time: 11 bytes
The int_mr_end_add interrupt occurs when the data transfer to the UDC2 endpoint is finished. In order to
confirm whether the entire data has been transferred from UDC2 to the USB host, check the mrepempty bit of
Master Status register.
endpoint of UDC2 (bus_sel of UDC2 EPx_Status register (bit14)) to the direct access
mode. It is prohibited to start DMAC when it is set to “Common bus access.”
This section describes the master transfer operation of UDC2AB.
When you start a master transfer, be sure to set the transfer setting of the relevant
Read EOP enable) are described here. Master Read operations will be as follows:
Master Read transfers when UDC2STSET<eopb_enable> is set to 1 (Master
EOP enable mode
1. Set Master Read Start Address and Master Read End Address registers.
2. Set the bits associated to the Master Read operation of DMAC Setting
3. UDC2AB starts the data transfer to the endpoint of UDC2. UDC2 transfers
4. When the Master Read transfer reaches the Master Read end address,
5. After the handling by the software ended, return to 1.
In case Master Read transfer size: 1035 bytes, and Max packet size: 512 bytes,
register and set 1 to the mr_enable.
the data to the IN token from the USB host.
UDC2AB asserts the int_mr_end_add interrupt.
TMPA901CM- 482
TMPA901CM
2010-07-29