TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 232

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:22]
[21:20]
[19:18]
[17:16]
[15:14]
[13:0]
[Description]
Bit
a. <memory_cmd>
Note:
3.
This register sets each command for external memory and external memory mode register.
This register sets the initial setting of external memory.
Determines the command required:
0y00 = Prechargeall
0y01 = Autorefresh
0y10 = Modereg or Extended modereg
0y11 = NOP
Use dmc_direct_cmd_5 to configure cas latency of DDR_SDRAM memory,
The setting of cas latency(CL) is different from SDR_SDRAM.
The CL setting value of memory controler must be 1 smaller than the CL setting
value of DDR_SDRAM memory.
Examples:
dmc_cas_latency_5 ← 0x00000004 (set memory controller CL = 2)
dmc_direct_cmd_5 ← 0x00080033
dmc_direct_cmd_5 (DMC Direct Command Register)
chip_nmbr
memory_cmd
bank_addr
addr_13_to_0
Symbol
Bit
WO
WO
WO
WO
Type
TMPA901CM-231
Undefined
Undefined
Reset
Value
(set DDR SDRAM memory CL = 3)
Read as undefined. Write as zero.
Always write 0y00
Determines the command required:
0y00 = Prechargeall
0y01 = Autorefresh
0y10 = Modereg or Extended modereg
0y11 = NOP
Bits mapped to external memory bank address bits when
command is Modereg access.
0y00 = bank0
0y01 = bank1
0y10 = bank2
0y11 = bank3
Read as undefined. Write as zero.
Bits mapped to external memory address bits [13:0] when
command is Modereg access.
Description
Address
(0xF431_0000) + (0x0008)
TMPA901CM
2010-07-29