TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 352

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

g. <BRK>
Note: When you set UARTxLCR_H, UARTxIBRD and UARTxFBRD, UARTxLCR_H must be set at the end.
register.
When this bit is set to 1, the UxTXD output remains LOW after the current character is
transmitted. For generation of the transmit break condition, this bit must be asserted
while at least one frame is or longer being transmitted. Even when the break condition is
generated, the contents of the transmit FIFO are not affected.
Table 3.13.2 is the truth table of the <SPS>, <EPS> and <PEN> bits of the UARTxLCR_H
enable(PEN)
When you update only UARTxIBRD or UARTxFBRD, UARTxLCR_H register must be set again.
Table 3.13.2 Truth table of UARTxLCR_H <SPS>, <EPS> and <PEN>
Parity
0
1
1
1
1
select(EPS)
Even parity
1
0
0
1
x
TMPA901CM- 351
Stick parity
(SPS)
select
x
0
0
1
1
Parity bit (transmitted or checked)
Not transmitted or checked
Even parity
Odd parity
1
0
TMPA901CM
2010-07-29