TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 503

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(6) INT_EP
(7) INT_RX_ZERO
(8) INT_SOF
(9) INT_NAK
(when the transaction finished normally). In that case, which endpoint the transfer
was made can be identified by checking INT_EP register. This interrupt will be
deasserted by writing 1 into the relevant bit (bit 6) of INT register, or by writing 1 into
all bits set in INT_EP register. INT register should be cleared at the point the interrupt
was recognized.
“H” is asserted only when Zero-Length data is received in the DATA-Stage. It will not
be asserted when Zero-Length data is received in the STATUS-Stage. Which endpoint
has received the data can be identified by reading the bits [11:8] of Command register
or checking INT_RX_DATA0 register. This interrupt will be deasserted by writing 1
into the relevant bit (bit 3) of INT register, or by writing 1 into all bits set in
INT_RX_DATA0 register. INT_RX_DATA0 register should be cleared at the point the
interrupt was recognized.
into the relevant bit (bit 4) of INT register. INT register should be cleared at the point
the interrupt was recognized.
host to devices every 1 ms in the Full-Speed transfers, and every 125
High-Speed transfers.
case, which endpoint has transmitted the NAK can be identified by checking INT_NAK
register. This interrupt will be deasserted by writing 1 into the relevant bit (bit 7) of
INT register, or by writing 1 into all bits set in INT_NAK register. By default, this flag
will not be asserted when NAK was transmitted. Therefore, you should write 0 into
the relevant endpoint of INT_NAK_MASK register to release the mask in order to use
this flag.
In endpoints other than Endpoint 0, asserts “H” when “ACK” was sent or received
“H” is asserted when Zero-Length data is received. In Control transfers, however,
Asserts “H” when SOF was received. This interrupt will be deasserted by writing 1
SOF is a packet indicating the start of a frame ( frame). It is transmitted from the
In endpoints other than Endpoint 0, asserts “H” when NAK is transmitted. In that
TMPA901CM- 502
TMPA901CM
2010-07-29
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