TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 633

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
STN64 gray
TFT16bit
others
STN64CR
Bit
Mode
Register
Name
3.18.4.2 Description of Registers
NoSpikeMode
CLFP_Inv
:CLLP_Inv
CLAC_Inv
LCP_Inv
G64_8bit
G64_en
Reserved
Note: When using STN 64-level grayscale mode, be sure to set LCLFP, LCLLP, LCLAC, and LCLCP identically with
Note1: For the LD bus switching mechanism, see Figure 3.18.5 LCDCOP Block Diagram LCDCOP Block Diagram.
Note2: For information about external 16-bit TFT signals, see Table3.18.5 LCD TFT panel signal multiplexing [TFT
15. STN64CR (LCDC Option Control Register)
Symbol
0y1 :
Use STN 64 gray circuits
0y0 :
Not Use STN 64 gray circuits
0y0 :
Not Use STN 64 gray circuits
Bit
the settings in the LCDC.
16bit Interface]
0x0000
Address
The following lists the registers:
(base+)
<G64_en>
Table 3.18.8 The setting of STN 64 gray and TFT16 bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
LCDC Option Control Register for STN 64
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Reset
Value
Register setting
TMPA901CM- 632
Invert vertical synchronization(=VIS of LCDC)
Invert horizontal synchronization (=HIS of LCDC)
Invert output enable (= IOE of LCDC)
0y0 : LCLAC output HIGH active in TFT mode
0y1 : LCLAC output LOW active in TFT mode
Invert panel clock (=IPC of LCDC)
Read as undefined. Write as zero.
Delete noise of CLCP of LCDC
0y0 :
0y1 :
Read as undefined. Write as zero.
0y0 : LCLFP pin HIGH active
0y1 : LCLFP pin LOW active
0y0 : LCLLP pin HIGH active
0y0 : LCLCP rising edge
0y1 : LCLCP falling edge
Refer to the table of Table 3.18.8 The setting of STN 64 gray
and TFT16 bit .
0y1 : LCLLP pin LOW active
0y0 : External 4bit LD Bus
0y1 : External 8bit LD Bus
0y1 :
0y0 :
External LD12=CLD12
External LD6 =CLD6
External LD6 =CLD16
External LD12=CLD17
invalid
valid
<G64_8bit>
Description
Address
Description
(0xF00B_0000) + (0x0000)
Base address
If LD[15:0] Function of Port P
and Port V are setted,
<G64_8bit> need be seted to
0y1, to ouput CLD17, CLD16
Note
0xF00B_0000
TMPA901CM
2010-07-29