TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 372

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

I2C0DA pin
I2C0CL pin
Interrupt request
I2C0SR<TRX>
I2C0SR<PIN>
2. Start Condition and Slave Address Generation
Note 1: Before writing a slave address to I2C0DBR, make sure that the bus is free by software.
Note 2: After a slave address is written and before a start condition is generated, another master may initiate transfer
to I2C0DBR. Writing 1 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<BB> and
I2C0CR2<PIN> causes a start condition, the slave address and direction bit to be sent out
on the bus. After a start condition is generated, it takes the t
to fall.
I2C0CL and I2C0SR<PIN> is cleared to 0. While I2C0SR<PIN> is 0, I2C0CL is pulled low.
Only when the acknowledge signal is returned from the slave device, I2C0SR<TRX> is
changed by hardware according to the direction bit upon generation of an I2CINT0
interrupt request.
CHK _ BB:
Programming example: Generating a start condition
Check that the bus is free (I2C0SR<BB> = 0).
Set I2C0CR1<ACK> to 1 and write the slave address and direction bit to be transmitted
Then, an I2CINT0 interrupt request is generated on the falling edge of the 9th clock of
operation. Therefore, after writing a slave address to I2C0DBR, check a bus free state again by software
within 98.0 s (the shortest transfer time in standard mode according to the I
shortest transfer time in fast mode according to the I
only after a bus free state is confirmed.
Start condition
Figure 3.14.5 Start condition and Slave address generation
r1
AND
CMP
BNE
(I2C0DBR) ←
(I2C0CR2) ←
1
2
←
(I2C0SR)
r1, #0x20
r1, #0x00
CHK _ BB
0xCB
0xF8
3
TMPA901CM- 371
Slave address + direction bit
4
5
; Check that the bus is free.
; Set the slave address to 0x65 and direction bit to 1.
; Set I2C0CR2<MST>, <TRX>, <BB>, <PIN> to 1.
2
C bus standard). A start condition should be generated
6
7
HIGH
8
2
C bus standard) or 23.7 s (the
period for the I2C0CL pin
9
ACK from slave
TMPA901CM
When the direction bit is 1
and ACK is returned,
I2C0SR<TRX> is cleared
to 0.
2010-07-29