TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 715

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

2. ADREG4H (AD conversion result higher-order register 4))
[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
[Description]
a. <ADR4[9: 2]>
Note : As ADREG4H to ADREG7H and ADREGSPH Registers are the same composition. Explain Register
Conversion setting of
channel x
They are AD conversion result higher-order bits 9 to 2.
ADR49
ADR48
ADR47
ADR46
ADR45
ADR44
ADR43
ADR42
About the address of ADREG4H to ADREG7H and ADREGSPH Register, please check Register Map.
ADREG4H only, the other Registers are same as ADREG4H.
Symbol
Bit
RO
RO
RO
RO
RO
RO
RO
RO
Type
ADREGxH
9
7
8
6
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
TMPA901CM- 714
Reset
Value
7
5
4
6
3
5
Read as undefined.
AD conversion result higher-order bit 9
AD conversion result higher-order bit 8
AD conversion result higher-order bit 7
AD conversion result higher-order bit 6
AD conversion result higher-order bit 5
AD conversion result higher-order bit 4
AD conversion result higher-order bit 3
AD conversion result higher-order bit 2
2
4
1
3
0
Always read as 0 when bits 5 to 2 are read.
Bit 0 is the AD conversion result storage flag <ADRxRF>.
Set to 1 when AD conversion settings are stored. Cleared
to 0 when the lower-order register (ADREGxL) is read.
Bit 1 is the overrun flag <OVRx>. Set to 1 when
conversion results are overwritten before reading the
both conversion result storage registers (ADREGxH,
ADREGxL). Cleared to 0 by flag read.
2
1
7
Address
Description
0
6
5
4
(0xF008_0000) + (0x0024)
3
2
ADREGxL
1
TMPA901CM
2010-07-29
0