TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 387

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

d. <PIN>
e. <I2CM>
f. <SWRES[1:0]>
Note: Refer to Section 3.14.6.3 “Serial Clock”.
being performed. Before clearing this bit, make sure that transfer operation is completely
stopped by reading the status register.
f
abort any ongoing transfer operation. All the settings except I2C0CR2<I2CM> are
initialized. (I2C0DBR is not initialized.)
PCLK
This bit is used to clear a service request for I
0y0: Invalid
0y1: Clear service request
This bit enables or disables I
0y0: Disable
0y1: Enable
The <I2CM> bit cannot be cleared to 0 to disable I
Writing 0y10 and then 0y01 to these bits generates a software reset (reset width = one
If a software reset occurs, the SCL and SDA lines are forcefully released (driven high) to
When generating a software reset, be sure to write 0 to I2C0CR2[7:4].
clock pulse).
TMPA901CM- 386
2
C operation.
2
C communication.
2
C operation while transfer operation is
TMPA901CM
2010-07-29