TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 343

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

4. UART1SR/ UART1ECR (UART1 Receive status register/ UART1 error clear register)
[31:4]
[3]
[2]
[1]
[0]
[31:0]
Bit
Bit
Note 1: The UARTxSR/UARTxECR register is the receive status register/error clear register. Receive status can also
Note 2: The receive data must be read first from UARTxDR before the error status associated with that data is read
be read from UARTxSR. If the status is read from this register, the status information for break, framing and
parity corresponds to the data read from UARTxDR prior to reading UARTxSR. The status information for
overrun is set immediately when an overrun condition occurs. A write to UARTxECR clears the framing, parity,
break and overrun errors. All the bits are cleared to 0 on reset.
from UARTxSR. This read sequence cannot be reversed because the status register UARTxSR is updated
only when the data is read from the data register UARTxDR. The status information can also be read directly
from the UARTxDR register.
OE
BE
PE
FE
Symbol
Symbol
Bit
Bit
RO
RO
RO
RO
WO
Type
Type
TMPA901CM- 342
0y0
0y0
0y0
0y0
Reset
Reset
Value
Value
Read as undefined.
Overrun error:
0y0: There is an empty space in the FIFO.
0y1: Overrun error flag
Break error
0y0: No error detected
0y1: Error detected
Parity error
0y0: No error detected
0y1: Error detected
Framing error
0y0: No error detected
0y1: Error detected
A write to this register clears framing, parity,
break, and overrun errors. The data value has
no significance.
The address of this register is the same as that
of the UART1SR register.
Address
Address
Description
Description
(0xF200_0000) + (0x0004)
(0xF200_0000) + (0x0004)
TMPA901CM
2010-07-29