TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 614

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:27]
[26]
[25:16]
[15]
[14]
[13]
[12]
[11]
[10:6]
[5]
[4:0]
Bit
[Description]
a. <PCD_HI>
Note1: This bit is usable TFT mode only.
Note2: This bit is usable STN mode only.
3.
HCLK frequency. A 10-bit divisor can be specified by combining PCD_HI (upper 5 bits) and
PCD_LO (lower 5 bits). LCLCP = HCLK/ (PCD + 2).
LCDTiming2 is the read/write register to control the LCDC timing.
The PCD_HI field is used to generate the LCD panel clock frequency by dividing the
PCD_HI
Reserved
CPL
IOE
IPC
IHS
IVS
ACB
Reserved
PCD_LO
Symbol
LCDTiming2 (Clock and Signal Polarity Control Register)
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
0y00000
0y0
0y0000000000
Undefined
0y0
0y0
0y0
0y0
0y00000
Undefined
0y00000
Reset
Value
TMPA901CM- 613
0y00000 to 0y11111
Read as undefined. Write as zero.
0y0000000000 to 0y1111111111
Read as undefined. Write as zero.
0y0: LCLAC output “H” active in TFT mode
0y1: LCLAC output “L” active in TFT mode
0y0: LCLCP rising edge
0y1: LCLCP falling edge
0y0: LCLLP pin “H” active
0y1: LCLLP pin “L” active
0y00000 to 0y11111
Read as undefined. Write as zero.
Value set for the higher 5 bits of panel clock frequency division
Number of clocks per line
Data enable signal invert setting (Note1)
Panel clock signal edge selection
Horizontal synchronization signal Invert setting
Vertical synchronization signal Invert setting
0y0: LCLFP pin “H” active
0y1: LCLFP pin “L” active
Bias invert frequency (Setting
Value set for the lower 5 bits of panel clock frequency division
Description
Address
1) (Note2)
(0xF420_0000) + (0x0008)
TMPA901CM
2010-07-29