TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 480

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.2.6 Reset
Software reset ( Power Detect Control<pw_resetb> )
Master channel reset (mr_reset/mw_reset bit of DMAC Setting register)
software reset with the values retained. As details are provided in the descriptions of
each register, refer to section 3.16.2.5 “Registers”.
needed.
mr_reset bit for the Master Read transfer block, only the relevant master blocks are
initialized and the UDC2AB register will not be initialized. For more information on
using each reset, see section 3.16.2.5 “(2) 5. UDMSTSET (DMAC Setting register).”
register) for DMAC master transfers.
Some bits of each register are initialized by hardware reset but not initialized by
When the USB bus power is detected, make software reset as initialization is
While the mw_reset bit is provided for the Master Write transfer block and the
UDC2AB supports software reset by the Power Detect Control<pw_resetb>.
It also supports master channel reset (mr_reset/mw_reset bit of DMAC Setting
TMPA901CM- 479
TMPA901CM
2010-07-29