TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 62

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

<PLLON>
PLL output: f
Lock-up timer
<LUPFLAG>
CPU clock f
<FCSEL>
PLL output: f
CPU clock f
<FCSEL>
<PLLON>
Note: When switching <FCSEL> from 1 to 0, a few clock cycles are required before f
FCLK
Setting example – 2: PLL stop
LUP:
PLL
the register write is completed. Therefore, it is necessary to first wait for the required clock cycles and then
execute the next instruction. More specifically, execute 10 NOP instructions.
FCLK
PLL
(SYSCR2)
Dummy instruction execution (Note)
(SYSCR3)
Switch from 192 MHz to 24 MHz
start
PLL operation and lock-up
替
Count up at f
←
←
TMPA901CM- 61
0x0000_0000
0x0000_0007
OSCH
During lock-up
PLL operation stop
; <FCSEL> = 0 (change from 192 MHz to 24 MHz)
; <PLLON> = 0
Lock-up end
Switch from 24 MHz to 192 MHz
After lock-up
替
FCLK
is changed to f
TMPA901CM
2010-07-29
OSCH
after