TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 281

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.11.4.2 Error Correction Methods
Hamming ECC
1. The calculated ECC and the ECC in the redundant area (Note 1) are rearranged, so
2. The two rearranged ECCs are XORed.
3. If the XOR result is 0, indicating an ECC match, the error correction process ends
4. If the XOR result contains only one ON bit, it is determined that a single-bit error
5. If every two bits of bits 0 to 15 and bits 18 to 23 of valid data in the XOR result are
6. For correction of the data, the line information in error is created from the line
Example: When the XOR result is 0y10_01_10_00_10_10_01_10_01_01_10_10
that the lower 2 bytes of each ECC represent line parity (LPR15: 0) and the upper 1
byte (of which the upper 6 bits are valid) represents column parity (CPR7: 2).
normally (no error). If the XOR result is other than 0, it is checked whether or not
the error data can be corrected.
exists in the ECC data itself and the error correction process terminates here (error
not correctable).
either 0y01 or 0y10, it is determined that the error data is correctable and error
correction is performed accordingly. If the XOR result contains either 0y00 or 0y11,
it is determined that the error data is not correctable and the error correction
process terminates abnormally.
parity of the XOR result and the bit information is created from the column parity
and then the error bit is inverted. The error correction is now completed.
The ECC generator generates 44 bits of ECC for a page containing 512 bytes of
valid data. The error correction process must be performed in units of 256 bytes
(22 bits of ECC). The following explains how to implement error correction on
256 bytes of valid data using 22 bits of ECC.
If the NAND-Flash memory to be used has a large-capacity page size (e.g. 2048
bytes), the error correction process must be repeated several times to cover the
entire page.
In this case, an error exists at address 0xD3. Note that this address is not an absolute address but a
relative address in 256 bytes. Due care must be used when correcting this error.
Convert two bytes of line parity into one byte. (10→1, 01→0)
Convert six bits of column parity into three bits. (10→1、01→0)
Line parity:
Column parity:
Error correction is performed by inverting the data in bit 5 at address 0xD3.
Binary
Example of Correctable XOR
10 01 10 00
10 10 01 10
01 01 10 10
TMPA901CM- 280
10 10 01 10 01 01 10 10
10 01 10
1
1
Result
1
0
Column parity
Line parity
0 1
1
5
0
0
1
10 11 10 00
10 10 01 10
01 01 10 10
1
Example of Uncorrectable
0xD3
XOR Result
Column parity
Line parity
→ Error in bit 5
TMPA901CM
2010-07-29