TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 12

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

SJ4
DMCBA0
SJ5
DMCBA1
SJ6
DMCCKE
SK0
DMCSDQM0
DMCDDM0
SK1
DMCSDQM1
DMCDDM1
SK4
SMCWEn
SL0
DMCSCLK
DMCDCLKP
SL1
DMCDCLKN
SL2
DMCAP
SL4
DMCDDQS0
SL5
DMCDDQS1
SL6
DMCCLKIN
Pin name
Note: Pin names "SA0 through SA7, …, and SR0 through SR4” are symbols used for convenience and are different
Number of pins
from general-purpose port functions “PA0 through PA7, …, and PV0 through PV7."
1
1
1
1
1
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input/Output
Input/Output
Input
Input/Output
Table2.2.1 Pin names and functions (2/6)
BANK0 strobe signal for SDR_SDRAM
BANK0 strobe signal for DDR_SDRAM
BANK1 strobe signal for SDR_SDRAM
BANK1 address strobe signal for DDR_SDRAM
Clock-enable signal for SDR_SDRAM
Clock-enable signal for DDR_SDRAM
－
Byte enable signal (D0 to D7) for SDR_SDRAM
Data mask signal (D0 to D7) for DDR_SDRAM
－
Byte enable signal (D8 to D15) for SDR_SDRAM
Data mask signal (D8 to D15) for DDR_SDRAM
－
Write-enable signal for NORF/SRAM/MROM
Clock signal for SDR_SDRAM
Positive phase clock signal for DDR_SDRAM
Not used
Negative phase clock signal for DDR_SDRAM
Address/Precharge signal for SDR_SDRAM
Address/Precharge signal for DDR_SDRAM
Not used
Data strobe signal (D0 to D7) for DDR_SDRAM
Not used
Data strobe signal (D8 to D15) for DDR_SDRAM
FB clock for SDR/DDR_SDRAM
TMPA901CM- 11
Function
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
For both MPMC0 and MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
When using MPMC0
When using MPMC1
－
For both MPMC0 and MPMC1
Remarks
TMPA901CM
2010-07-29