TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 61

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.5.4
3.5.5
Examples of the PLL start and stop settings are as follows:
(1) Clock gear
System Clock Controller
PLL Clock Multiplier
other built-in I/Os (f
SYSCR1<GEAR2:0> to change the high speed clock gear to 1, 2, 4, or 8-speed (fc, fc/2, fc/4,
or fc/8) to reduce power consumption.
therefore, frequency of the CPU clock f
24 MHz oscillator is connected to the X1 and X2 pins, the frequency of f
MHz when reset operation is executed.
PLL, it is possible to lower the oscillator frequency and make the internal clock faster.
necessary to configure the SYSCR2, SYSCR3 and SYSCR4 registers when using the PLL.
operation is enabled, and the time required is called lock-up time.
time is approximately 164 s when f
Setting example – 1: PLL start
LOCKUP:
The system clock controller generates a clock to be supplied to the CPU core (f
Reset operation switches the mode to PLL-OFF, and <GEAR2:0> is initialized to 0y000;
The PLL outputs f
Since the PLL is initialized to the halt state when reset operation is executed, it is
As with an oscillator, this circuit requires time to stabilize the f
A 12-stage binary counter can be used to check the lock-up time. For example, lock-up
fc, fc/2, fc/4, or fc/8.
consumption.
By using the clock gear selection register SYSCR1<GEAR2:0>, the gear can be set to
Changing f
An example of clock gear switching is as follows:
;
(SYSCR1)
[Setting example]
SYSCR4
SYSCR3
SYSCR2
LDR
AND r0,r0,r1
LDR r1, = 0x01
CMP r0 ,r1
BNE LOCKUP
(SYSCR2)
r1, = 0x01
FCLK
PLL
HCLK
clock signals whose frequency is 6 or 8 times the f
by using the clock gear contributes to reduction of power
). With the f
←
←
→
←
TMPA901CM- 60
←
0x00000065
0x00000087
r0
0x00000002
OSCH
OSCH
FCLK
= 25 MHz.
0x0000_0011
or f
will be the same as f
PLL
; Set the constant of PLL x8
; Operation is activated with PLL x8
; <LUPFLAG> == 1?
;
; r0 ≠r1 ,
; <FCSEL> = 1 (change from 24 MHz to 192 MHz)
clock as an input, it is possible to use
jump to LOCKUP
; switch f
OSCH
. For example, when a
PLL
FCLK
clock signals after
OSCH
to 1/8.
FCLK
TMPA901CM
. By using the
2010-07-29
becomes 24
FCLK
) and