TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 521

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

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[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
[Description]
m_nak
m_ep
m_ep0
m_sof
m_rx_data0
m_status
m_status_nak
m_setup
i_nak
i_ep
i_ep0
i_sof
i_rx_data0
i_status
i_status_nak
i_setup
a. <m_nak>
b. <m_ep>
Note: The lower byte (bits 7-0) will be cleared by writing 1 to the relevant bits.
Symbol
Bit
(3) Interrupt Control registers
1.
Sets whether or not to output "i_nak (bit 7)" to the INT_NAK pin.
0y0: Enable (output)
0y1: Disable (no output)
Sets whether or not to output "i_ep (bit 6)" to the INT_EP pin.
0y0: Enable (output)
0y1: Disable (no output)
UD2INT (INT register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Reset
Value
TMPA901CM- 520
Read as undefined. Write as zero.
Sets whether or not to output "i_nak (bit 7)" to the INT_NAK pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_ep (bit 6)" to the INT_EP pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_ep0 (bit 5)" to the INT_EP0 pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_sof (bit 4)" to the INT_SOF pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_rx_data0 (bit 3)" to the
INT_RX_ZERO pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_status (bit 2)" to the INT_STATUS
pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_status_nak(bit1)" to the
INT_STATUS_NAK pin.
0y0: Enable (output) 0y1: Disable (no output)
Sets whether or not to output "i_setup (bit 0)" to the INT_SETUP
pin.
0y0: Enable (output) 0y1: Disable (no output)
This will be set to 1 when NAK is transmitted by EPs except EP0.
This will be set to 1 when transfers to EPs other than EP0 have
successfully finished
This will be set to 1 when the transfer to EP0 has successfully
finished.
This will be set to 1 when the SOF-token is received or after 1
frame-time was counted in the create_sof mode.
This will be set to 1 when Zero-Length data is received.
This will be set to 1 when the STATUS-Stage has successfully
finished in Control transfers at EP0.
This will be set to 1 when “NAK” is returned during packet reception
of the STATUS-Stage during Control-RD transfer to EP0.
This will be set to 1 when the Setup-Token was received in Control
transfers at EP0.
Description
Address = (0xF440_0000) + (0x0220)
TMPA901CM
2010-07-29