TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 225

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Note: Clock Suspend Mode function and Power Down mode cannot be used concurrently.
(2) DMC Function operation
(a) Arbiter operation
(b) Memory manager operation
(c) Memory interface operation
(d) Low Power function
According to use, there are three kinds of built-in FIFOs.
DMC provide 2 kinds of Low Power modes.
1. read/write access arbitration
2. For read accesses, QoS (Quality of Service) is provided.
3. Hazard processing
4. Monitoring the state machine and select an entry of the proper pipeline.
1. Monitor and control DMC circuit
2. Issuing direct comand
3. Auto Refresh function is provided
1. command FIFO: 2 words
2. read data FIFO:10 words
3. write data FIFO:10 words
1. Set dmc_memc_cmd_3 register to realize Low_power (Self Refresh Mode).
2. Set dmc_memory_cfg_3 register, stop memory clock (DMCCLK) or as no memory
As the FIFO sizes of either read or write FIFO is 10 words.
For one transfer, the max size is 8 words.
actual access procedure to memory is executed in the instruction order.
However, if multiple bus master access to an external memory, the read and
write data will be stored temporary into independent buffer and be executing by
priority circuit. Therefore, the read and the write instruction may switch
execution sequence. So please coordinate a variety of sequences, e.g. making an
enough time for next instruction, checking whether or not previous execution is
finished, the common-use memory data uses the internal memory and so on.
access, CKE is set to invalid (CKE = low).
Set Auto Refresh timing by 15bit counter.
When selfsame stand-alone bus master access to an external memory, the
NOP
PRECHARGEALL
AUTOREFRESH
MODEREG
EXTENDED MODEREG
TMPA901CM-224
TMPA901CM
2010-07-29