TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 276
TMPA901CMXBG
Manufacturer Part Number
TMPA901CMXBG
Description
Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
Manufacturer
Toshiba
Datasheet
1.TMPA901CMXBG.pdf
(858 pages)
Specifications of TMPA901CMXBG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
-
Rom Type
ROMless
Ram (kbytes)
32
Number Of Pins
177
Package
BGA
Vcc
3V
Tft Lcd Controller
Y
Touchscreen Controller
Y
Usb Host Fs With Phy
Y
Usb Device Hs With Phy
Y
Sd Host Controller
-
Cmos Image Sensor Interface
-
I2s
1
Ssp (ch) Spi
1
I2mc/sio (ch)
1
Uart/sio (ch)
2
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
8
10-bit Ad Converter
4
12-bit Da Converter
-
16-bit Timer / Counter
6
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
Y
Low-power Modes
Y
Lead Free Status / Rohs Status
Details
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Manufacturer
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NDFMCR1<ALS>
NDRB
NDREn
FIFO to be read by the DMAC
FIFO used for read from the
NAND-Flash
DMAC end interrupt
register
c.
Note: Please use the DMA function for the data read that uses the autoload function.
Data writing from the built-in RAM to the NAND-Flash memory in page units
performed similarly to data reading from the NAND-Flash. For execution, perform the
settings described in steps (1) and (2) below.
are full, the autoload function is suspended for that duration.
The following shows a conceptual timing chart of the data read timing by DMA.
The following is a description of data writing using the Autoload function that is
If DMAC cannot read the data from a FIFO of the NDFC when both FIFO-0 and FIFO-1
(1) Assign the NDFC to an arbitrary channel of the DMA controller and set the
DMACC0SrcAddr
DMACC0DestAddr
DMACC0Control
DMACC0Configuration ← <FlowCntrl> = 0y001(Memory to Peripheral),
relevant registers.
The following is an example in which the NDFC is assigned to DMAC channel 0:
1
2
0
16
← <Swidth[2:0]> = 0y010 (32 bits),
← Address of the built-in RAM
← Address of NDFDTR
TMPA901CM- 275
<SBSize[2:0]> = 0y001 (4 beats),
<TransferSize[11:0]> = 0x80 (512 Byte/4 Byte)
17
<Dwidth[2:0]> = 0y010 (32 bits),
<ITC> = 1 (DMA termination interrupt is enabled.)
0
18
1
32
33
1
34
0
48
497
0
498
1
512
TMPA901CM
2010-07-29
1
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