TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 587

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

WS cycle
I2SRSLVON = 0x0
FIFO 1 set
Receive circuit State machine
[31:1]
[0]
[Description]
a. <I2SRx_SLAVE>
Bit
Note: The current status of internal operation can be read by I2STST<I2STxSTATUS>
2 process
4.
PRE_SBY
When this bit is set (0
follows:
In the ACT state, data is captured into the FIFO.
When this bit is cleared (1
as follows:
In the SBY state, no data is captured into the FIFO even when input data is present.
I2SRSLVON (Rx I
I2SRx_SLAVE
Bit Symbol
SBY (standby)
ACT
PRE_SBY
State that can write to
FIFO of Transmission
circuit
2
S Slave Control Register)
R/W
Type
SBY
ACT
1), the internal status (I2SRST<I2SRxSTATUS>) changes as
TMPA901CM- 586
PRE_ACT
0), the internal status (I2SRST<I2SRxSTATUS>) changes
SBY
Undefined
0y0
Reset
Value
ACT
Observe I2SRSLVON = 0x1
WS edge
PRE_ACT
Read as undefined. Write as zero.
Write the FIFO for receiver 0y0: OFF
0y1: ON (FIFO write enabled)
WS cycle
Address
Description
2 process
(0xF204_0000) + (0x0024)
TMPA901CM
2010-07-29