TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 419

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Note1)
Note2)
With this setting, during idle periods:
master signal driven by LOW notifies of the start of transmission. This enables the
slave data in the SP0DI input line of the master.
the SP0DO pin. Both the master data and slave data are now set. When another half of
SP0CLK has passed, the SP0CLK master clock pin becomes HIGH. After that, the data
is captured at the rising edge of the SP0CLK signal and transmitted at its falling edge.
In the single word transfer, the SP0FSS line will return to the idle HIGH state when
all the bits of that data word have been transferred, and then one cycle of SP0CLK has
passed after the last bit was captured. However, for continuous transfer, the SP0FSS
signal must be pulsed at HIGH between individual data word transfers. This is
because change is not enabled when the slave selection pin freezes data in its
peripheral register and the <SPH> bit is logical 0. Therefore, to enable writing of serial
peripheral data, the master device must drive the SP0FSS pin of the slave device
between individual data transfers. When the continuous transfer is complete, the
SP0FSS pin will return to the idle state when one cycle of SP0CLK has passed after the
last bit is captured.
SPI (continuous transfer, <SPO>
•The SP0CLK signal is forcedly set to Low
• SP0FSS is forcedly set to High
• The transmit data line SP0DO is arbitrarily set to LOW.
When a half of the SP0CLK period has passed, valid master data is transferred to
SP0FSS
SP0CLK
SP0DO
If the SSP is enabled and valid data exists in the transmit FIFO, the SP0FSS
SP0DI
When transmission is disable , SP0DO terminal doesn’t output and is high impedance status. This
terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high
impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage
level.
LSB
LSB
Hi-Z(Note2)
TMPA901CM- 418
MSB
MSB
4 to 16bit
0 & <SPH>
LSB
LSB
0)
Hi-Z(Note2)
MSB
MSB
TMPA901CM
2010-07-29